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Design of Pre-Emphasis Pulses for Large Memory Arrays with Minimal Word-Line Delay Time
http://hdl.handle.net/10297/00026465
http://hdl.handle.net/10297/0002646525412c68-9da0-47d1-82f4-4e140a94d1ab
名前 / ファイル | ライセンス | アクション |
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190509001 (452.6 kB)
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Item type | 会議発表論文 / Conference Paper_01(1) | |||||
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公開日 | 2019-05-09 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | Design of Pre-Emphasis Pulses for Large Memory Arrays with Minimal Word-Line Delay Time | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
資源タイプ | conference paper | |||||
著者 |
Matsuyama, Kazuki
× Matsuyama, Kazuki× Tanzawa, Toru |
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書誌情報 |
en : 2019 IEEE International Symposium on Circuits and Systems (ISCAS) 発行日 2019-05-01 |
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出版者 | ||||||
出版者 | IEEE | |||||
権利情報 | ||||||
権利情報 | © 2019 IEEE. | |||||
権利情報 | ||||||
権利情報 | Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
NDC | ||||||
主題Scheme | NDC | |||||
主題 | 541 | |||||
注記 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 2019 IEEE International Symposium on Circuits and Systems (ISCAS) Date of Conference: 26-29 May 2019 Conference Location: Sapporo, Japan |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 21581525 | |||||
ISBN | ||||||
識別子タイプ | ISBN | |||||
関連識別子 | 9781728103976 | |||||
出版者DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | 10.1109/ISCAS.2019.8702295 | |||||
フォーマット | ||||||
内容記述タイプ | Other | |||||
内容記述 | application/pdf | |||||
著者版フラグ | ||||||
出版タイプ | AM | |||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa |