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A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter
http://hdl.handle.net/10297/2078
http://hdl.handle.net/10297/20789ab28822-5ed9-4349-8b5d-36639c32969a
名前 / ファイル | ライセンス | アクション |
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080519001.pdf (661.3 kB)
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Item type | 学術雑誌論文 / Journal Article_01(1) | |||||||
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公開日 | 2008-05-19 | |||||||
タイトル | ||||||||
言語 | en | |||||||
タイトル | A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter | |||||||
言語 | ||||||||
言語 | eng | |||||||
資源タイプ | ||||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||
資源タイプ | journal article | |||||||
著者 |
Inokawa, Hiroshi
× Inokawa, Hiroshi
WEKO
816
× Takahashi, Yasuo× Degawa, Katsuhiko× Aoki, Takafumi× Higuchi, Tatsuo |
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書誌情報 |
IEICE transactions on electronics 巻 E87_C, 号 11, p. 1818-1826, 発行日 2004-11-01 |
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出版者 | ||||||||
出版者 | Institute of Electronics, Information and Communication Engineers | |||||||
権利情報 | ||||||||
権利情報 | (c)IEICE | |||||||
NDC | ||||||||
主題Scheme | NDC | |||||||
主題 | 541 | |||||||
ISSN | ||||||||
収録物識別子タイプ | ISSN | |||||||
収録物識別子 | 09168524 | |||||||
EISSN | ||||||||
収録物識別子タイプ | ISSN | |||||||
収録物識別子 | 17451353 | |||||||
NII論文ID | ||||||||
関連タイプ | isIdenticalTo | |||||||
識別子タイプ | NAID | |||||||
関連識別子 | 110003214797 | |||||||
NII書誌ID | ||||||||
収録物識別子タイプ | NCID | |||||||
収録物識別子 | AA10826283 | |||||||
関連サイト | ||||||||
識別子タイプ | URI | |||||||
関連識別子 | http://www.ieice.org/ | |||||||
関連名称 | http://www.ieice.org/ | |||||||
フォーマット | ||||||||
内容記述タイプ | Other | |||||||
内容記述 | application/pdf | |||||||
著者版フラグ | ||||||||
出版タイプ | VoR | |||||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 |